Re: gEDA-user: DRC check workaround for outline layer

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Wed, 2010-11-24 at 11:06 +0100, Kovacs Levente wrote:
> On Tue, 23 Nov 2010 15:56:39 +0000
> Peter Clifton <pcjc2@xxxxxxxxx> wrote:
> 
> > This is probably not something we'd commit as is to PCB, as for some
> > cases, DRC warnings on the outline layer could be useful, but Bdale
> > was looking for something along these lines on IRC yesterday.
> 
> I'd love to see that patch in HEAD. Or maybe that version, which looks for
> layer attributes.

I recalled there was a patch someone write which looked for attributes,
but when I trawled through the Sourceforge mire for that patch, I
couldn't find it, so knocked the above one out.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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