gEDA-user: Several Questions re. iverilog & geda-user

[f m <fma2000ca@yahoo.com>]

Hello,

This is a rather long email, so here is
a summary:

 - Quest#1: Mailing list search engines

 - Description of My System and iverilog0.5
            (Not really a question)

 - Quest#3: iverilog Binary gives vvp error

 - Quest#4: make_check & iverilog/vpp errors
            in source compiled version

 - Quest#5: Will iverilog meet my needs (when
            I get it running)

Question 1: Mailing list search engines
----------------------------------------
I've been trying to diligently search FAQs &
mailing list archives before posting.  One that
which really stands out is that it is very
slow to search through the archives right
now (though I don't doubt it would be much
worse if someone hadn't put the time and effort
to make it the way it is now).  cygwin has a
search engine (not sure of it's a majordomo 
thing or their own thing).  It's not ideal, but
it provides some way to quickly going through
lots of scattered material.  Would it be
easy to set up a search engine like those in
newsgroups, where you specify a boolean combination
of words and phrases to search in the body or
header fields?

My System
----------
My system is a Dell Inspiron 8000, pentiumIII,
WinME.  With the most recent cygwin installed
last night (setup.log says version 2.78.2.9).
I am using iverilog version 0.5.  I tried
precompiled binary as well as compiling source
under cygwin.  No attempt to install mingw due
to lack of time (seriously, not just trying to
avoid work, because by golly, it's actually
quite cool).  Version 0.5 means that I shouldn't
have any vpi problems described in the FAQ,
especially since I didn't move any file trees
(right?)....especially since I used only
default locations for install.  This is c:\iverilog
for precompiled binary, and whatever the
defaults are for cygwin, which I can't recite
here because I uninstalled it to try the
precompiled binary again.  I believe it was
something like /usr/local .

Question 2:
Binary version of iverilog gives vvp error
----------------------------------------------
I've been spending the weekend trying to get
verilog simulation functionality (I don't
really need synthesis ability right now).
The precompiled binaries for win32 run fine
on the Hello World example, but when I run vvp
on my own design, which uses alot of behavioural
modules from a custom library, I get the error
message the "Vvp caused an error in vvp.exe",
and it exits.  The behavioural models contains
none of the nitty gritty stuff which iverilog
doesn't support, the code being quite simple
(cycle accurate all-synchronous), and I've looked
at it myself.  In fact, I can say that the stuff
that isn't supported by iverilog is stuff I don't
really know anyways (and isn't in the modules I
use).  How can I begin trying to track the cause
of the error?

Question 3: "make check" error in source compilation
----------------------------------------------------
Here is an excerpt of the key error:

   make[1]: Entering directory        
     
`/cygdrive/c/WINDOWS/Desktop/iverilog0.5/verilog-
      0.5/vvp'
   ./vvp -M../vpi ./examples/hello.vvp |
     grep 'Hello, World.'
   system: Unable to locate vpi_register_sim$display:
      This task not defined by any modules. I cannot
      compile it.
   ./examples/hello.vvp: Program not runnable,
      1 errors.
   make[1]: *** [check] Error 1

The "make check" output ends with:

   c++ -o check  -fno-exceptions -I. -I./vvm
      -I./vpip -Lvvm -Lvpip check.cc -lvvm -lvpip 
   ./check | grep 'Hello, World'
   system.vpi: Unable to locate vpi_register_sim
   make: *** [check] Error 1

I grep'd the file tree for vpi_register_sim and
looked at the code to try to get a clue, but
couldn't really figure out what it was about
(which doesn't surprise me, as I've written
much simpler numerical simulation code before,
also stopped looking familiar after a few days).

None of the previous "configure" and "make" steps
had any error messages, though the "make" output
had warnings about a switch statement not covering
all cases of an ennumerated type in stub.c; this
sounds harmless (I looked at the code without much
understanding).

I also did a "c++ --help" at the wygwin bash prompt to
see if it was gnu c++.  It deferred bug reports to
www.gnu.org/software/gcc/bugs.html, so it looks like
gnu.  (At a previous attempt, I changed all c++ to
g++ in all scripts, ran configure, and went through
all scripts to change all c++ that crept through;
didn't seem to make any difference, though I was a
bit foggy about the correctness of doing that).  It
also doesn't make any difference on the error
whether I specify "--without-ipal" for "configure".
Finally, I changed some makefile/configure references
from Hello.v to Hello.vl to avoid some errors about
the nonexistence of Hello.v (and sqrt.v to sqrt.vl),
though I doubt that would have broken the script.  I
ignored the fact that there was also a Hello2.v.

So I crossed my fingers and hoped that the
"check test" error would magically turn out to be
benign.  I went ahead with "make install", and saw
no errors or warnings.  "iverilog" gives the
following vpp-related errors for both designs
(Hello World, as well as my own design using
proprietary library modules).......

Question 4:
Error: target_design entry point is missing
---------------------------------------------
A synopsis of the error message from iverilog is:

    CODE GENERATION -t dll ...
    /usr/local/lib/ivl/vvp.tgt: error:
        target_design entry point is missing.
    error: Code generation had errors.
    translate: /usr/local/lib/ivl/ivlpp
        -v -L Hello.vl | /usr/local/lib/ivl/ivl
        -v     -tdll -fDLL=/usr/local/lib/ivl/vvp.tgt
        -fVVP_EXECUTABLE=
            /usr/local/lib/ivl/../../bin/vvp
        -Fcprop -Fnodangle   -oHello.vvp -- -

For Hello World, this happens regardless of whether
I specify -smain and/or -mmain switches to iverilog.

So there it is.  That was a weekend of investigation.
Now I'm out of ideas of how next to troubleshoot this.
Thanks for any suggestions.

Question 5: Is this the right "simulator"?
--------------------------------------------
After all that investment, I'm still not even
sure that iverilog was designed to do what I
want (it is most promising looking free verilog
simulator I can find on the web).  However, I
did read warnings that it was intended more for
synthesis and feeding into backend tools.  I
have no desire to do synthesis, just see how
my design works when I string together a few
behaviourally modelled modules representing
blocks in my target system.  I only care about
cycle-accurate all-synchronous functionality.
I assume that since the verilog is pretty simple,
it won't matter that it isn't really targetting
a xilinx device.  And it looks like I can use
gtkwave to see the simulation output, saved via
VCD.  But I haven't really been able to get my
design to simulate to confirm that the simulator
does what I want.

I realize that silos and modelsim+xilinx has
evaluation versions of their software, but I'm
not interested in just evaluating software with
all sorts of size restrictions and inability to
save stuff.  Beggars can't be choosers, but
hopefully, iverilog does what I need.  I was
advised about the existence of verilogger (thanks,
Mike), but since it has no-save restrictions, I
would like to try getting iverilog working before
investing more time on alternatives.  As I'm sure
is the case with most other people, I lack time to 
properly investigate all the possibilities, and
one weekend was already spent on the
modelsim/xilinx evaluation software.

So, thanks in advance if anyone can give me the
heads up on whether I should be looking to iverilog
for my particular needs.

Thanks for any advice on the above questions.

Fred
fma@doe.carleton.ca
fma2000ca@yahoo.com



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