gEDA-user: Icarus Verilog delay specification problem

["Aleksandar B. Samardzic" <a.samardzic@matf.bg.ac.yu>]

Could someone please advise what's wrong with following code:

--- my_and2.v --------------
module my_and2 (out, a, b);
   output out;
   input  a, b;

   assign #5 out = a & b;
endmodule


module stimulus;
   wire out;
   reg 	a, b;

   my_and2 _my_and2 (out, a, b);

   initial
     begin
	a = 1'b0; b = 1'b0;
	#50 a = 1'b1;
	#50 b = 1'b1;
	#50 a = 1'b0;
	#50 b = 1'b0;
	#50 $dumpoff; $finish;
     end
   
   initial
     begin
	$dumpfile ("out.vcd");
	$dumpvars (1, stimulus);
     end
endmodule
----------------------------

After compiling above with Icarus Verilog 0.5 (iverilog -Wall -o
my_and2 my_and2.v) and running the executable, there is no delay
between change of input signals a or b and update of output signal
out. I'm using GTKWave to examine VCD file and I was also have a look
into out.vcd file and there are no delays there. I've tried also to
replace line:
    assign #5 out = a & b;
with:
    and #(5) and0(out, a, b);
but with same result.

Thanks.