The answer to your question about the handling of state machines depends on the synthesiser. My experience with Synplify has shown that it does not generate any kind of extra `checking' logic to trap these cases., eg. The default statement gets ignored. (I have not checked with the latest version, the last time I checked was at about Version 6.) When the Synopsys FPGA Express tool was on the market, it was capable of generating this kind of logic, and it would if you included a default clause in the state machine, and set the appropriate synthesis option.
As for what happens with no reset, I am stumped, I had not thought about that one before. But you are probably suspecting that this case is not handled well either? In the case of CPLD's, at least the older ones, when you implemented the logic on the chip, if you wanted a register to reset high, you had to use the inverted output, and feed the D input with inverted logic, so, even in the absense of a proper reset pulse, the power on reset inside the chip would do the right thing, probably.
Mike
John Sheahan wrote:
Karel Kulhavý wrote:>>What does a default: statement do?
>>What happens with no reset?
>>what happens with races or cosmic belches?
--
-------------------------------------------------- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek --------------------------------------------------