Re: gEDA-user: General ground/power plane design questions

[Dan McMahill <dan@mcmahill.net>]

On Wed, Oct 20, 2004 at 09:41:40AM -0400, Randall Nortman wrote:

> I'm designing a simple microcontroller board -- 4-layers, with ground
> and power (+5V) planes, to reduce noise.  The board will have a 16MHz
> AVR microcontroller, which is by far the highest frequency that ought
> to be going over any traces.  There are also analog inputs feeding
> into peripheral ADC's, connected to the AVR via SPI (running at less
> than 1MHz; probably 125kHz), some other peripherals on the I2C bus
> (running at 100kHz), and two serial interfaces (one RS232 and one
> RS485) running at less than 100kHz.  Almost everything will be surface
> mount, with the exception of connectors, jumper blocks, and some
> low-power solid state relays (kept well away from noise-sensitive
> stuff).

Luckily, nothing is running too fast which will help.  One thing
you didn't mention is the desired resolution of the ADC's.  The
challenges surrounding a 20 bit ADC are significantly different
than an 8 bit ADC.

> The good news is that I'm measuring what ought to be very
> low-frequency signals on the analog inputs (I don't care about
> anything over 10Hz, really), so I'm going to fake a low-pass filter by
> averaging multiple samples together.  (I want to keep the number of
> discrete components down, so I think this is better than an actual RC
> low-pass filter, though perhaps I'm missing something important.)  So
> what really concerns me is not noise on the analog portions, but noise
> on all the digital lines -- SPI, I2C, and the two UARTs.

put a simple 1 pole RC filter at the ADC inputs anyway to avoid
aliasing of "noise" from the digital stuff and any other wideband
noise which may be present on those inputs.


> So, now that you know what I'm trying to do, here are the questions:
> 
> 1) What's the best arrangement for the power planes?  Everything I've
>    read seems to indicate that they should be in the middle layers,
>    right next to one another, which provides some extra capacitance
>    between them and also shields the two signal layers from one
>    another.  But it seems to me that it might be a good idea to use
>    the bottom layers, to shield the board from any RF noise
>    originating outside of the board.  Perhaps it's better just to rely
>    on a grounded chassis to handle outside noise?  What if I want to
>    stack the boards on top of each other?  Will, say, 1.5" separation
>    be enough to eliminate any stray RF between the boards?  Also, does
>    it matter which plane (ground or supply) is closer to the component
>    side?  I figure that the component side should be used for the
>    higher-speed signals, so that they don't ever have to go through
>    vias, and the bottom side should be for the less sensitive stuff.
>    (I expect almost all the components, except maybe for some
>    resistors or caps, to be on the component side.)

Put the ground and power planes on the internal layers.  Also put
the ground plane closer to the component layer.  This is because
your circuits running on the top of the board are likely to have
their signals referenced to ground!  Putting the power plane on
top can cause some painful to debug issues.


> 2) I would like to be able to extend the SPI and I2C buses between
>    stacked boards for short distances (perhaps three boards stacked
>    1.5" apart with about 4" total cable length).  I'm thinking that
>    flat ribbon cable with every other conductor attached to ground
>    should provide enough crosstalk dampening for such short distances.
>    Does this seem reasonable, or am I going to have reflection
>    problems?  (The boards themselves will have traces up to about 5"
>    long carrying these signals, which also needs to be considered.)

I'd just put 100 ohms or so in series with the drivers.  At the speeds
you're running at for the SPI and I2C, you can afford to slow down the
edges enough to make your cable more or less look like a lumped circuit.


With regards to breaking up your planes, you could refer to the ADC
data sheets and/or app notes to see if they recommend anything.  If you
do end up breaking up your ground and/or power planes, the thing to 
watch for is really figuring out where your return currents must
flow.  For example, suppose you have a digital driver that drives
a piece of interconnect and ultimately a load which has a fair amount
of capacitance.  When the driver goes low, current flows out of the
load, through the trace, through the driver, into the ground pin
of the driver, through the ground metal, and back to the load.  
It is important that you pay attention to the "ground pin of
the driver, through the ground metal, and back to the load" part.
Cutting the ground plane in a good place can make that current
go where you want it and cutting in a bad place can cause
problems.  Same comments apply on a rising edge.  Current
flows from the driver power pin, through the driver, through
the interconnect to the load, through the load into its
ground connection, through ground back hopefully to the driver
bypass capacitor.  


-Dan

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