gEDA-user: General ground/power plane design questions

[Randall Nortman <geda-lists@wonderclown.org>]

Unlike my last plane question, this has nothing in particular to do
with geda or pcb -- I'm soliciting advice about PCB design in general.
I've been following this list for a while, and there seem to be quite
a few knowledgeable people here, which is what makes me think this is
a good place to ask.  However, feel free to tell me to take it to
another forum (suggestions welcome), or simply ignore me.

I'm designing a simple microcontroller board -- 4-layers, with ground
and power (+5V) planes, to reduce noise.  The board will have a 16MHz
AVR microcontroller, which is by far the highest frequency that ought
to be going over any traces.  There are also analog inputs feeding
into peripheral ADC's, connected to the AVR via SPI (running at less
than 1MHz; probably 125kHz), some other peripherals on the I2C bus
(running at 100kHz), and two serial interfaces (one RS232 and one
RS485) running at less than 100kHz.  Almost everything will be surface
mount, with the exception of connectors, jumper blocks, and some
low-power solid state relays (kept well away from noise-sensitive
stuff).

The good news is that I'm measuring what ought to be very
low-frequency signals on the analog inputs (I don't care about
anything over 10Hz, really), so I'm going to fake a low-pass filter by
averaging multiple samples together.  (I want to keep the number of
discrete components down, so I think this is better than an actual RC
low-pass filter, though perhaps I'm missing something important.)  So
what really concerns me is not noise on the analog portions, but noise
on all the digital lines -- SPI, I2C, and the two UARTs.

Nevertheless, I do intend to separate the analog and digital ground
and supply planes, while keeping them on the same layer.  That is,
there will be non-overlapping copper regions for each, connected
together at one point.  I gather this is pretty standard, although I'm
not sure how to handle the fact that the ADCs are both analog and
digital.  I guess I'll just try to guess which parts of the chip are
doing which based on the pin functions, and separate the planes along
the best dividing line I can discern.

So, now that you know what I'm trying to do, here are the questions:

1) What's the best arrangement for the power planes?  Everything I've
   read seems to indicate that they should be in the middle layers,
   right next to one another, which provides some extra capacitance
   between them and also shields the two signal layers from one
   another.  But it seems to me that it might be a good idea to use
   the bottom layers, to shield the board from any RF noise
   originating outside of the board.  Perhaps it's better just to rely
   on a grounded chassis to handle outside noise?  What if I want to
   stack the boards on top of each other?  Will, say, 1.5" separation
   be enough to eliminate any stray RF between the boards?  Also, does
   it matter which plane (ground or supply) is closer to the component
   side?  I figure that the component side should be used for the
   higher-speed signals, so that they don't ever have to go through
   vias, and the bottom side should be for the less sensitive stuff.
   (I expect almost all the components, except maybe for some
   resistors or caps, to be on the component side.)

2) I would like to be able to extend the SPI and I2C buses between
   stacked boards for short distances (perhaps three boards stacked
   1.5" apart with about 4" total cable length).  I'm thinking that
   flat ribbon cable with every other conductor attached to ground
   should provide enough crosstalk dampening for such short distances.
   Does this seem reasonable, or am I going to have reflection
   problems?  (The boards themselves will have traces up to about 5"
   long carrying these signals, which also needs to be considered.)

Thank you very much for any advice you can provide, and once again I
apologize if asking for such advice here is inappropriate.

Randall Nortman