Re: gEDA-user: General ground/power plane design questions

["J.D. Bakker" <bakker@thorgal.et.tudelft.nl>]

> I'm designing a simple microcontroller board -- 4-layers, with ground
> and power (+5V) planes, to reduce noise.  The board will have a 16MHz
> AVR microcontroller, which is by far the highest frequency that ought
> to be going over any traces.  There are also analog inputs feeding
> into peripheral ADC's, connected to the AVR via SPI (running at less
> than 1MHz; probably 125kHz), some other peripherals on the I2C bus
> (running at 100kHz), and two serial interfaces (one RS232 and one
> RS485) running at less than 100kHz.  Almost everything will be surface
> mount, with the exception of connectors, jumper blocks, and some
> low-power solid state relays (kept well away from noise-sensitive
> stuff).
As others have mentioned, you are WAY over-engineering this (but 
that's hardly ever a bad starting point). You don't mention the 
resolution you are aiming for, or the source signal level / 
impedance, or how long the lines to your sensors will be. Many things 
have been mentioned already in this thread, just wanted to 
add/re-emphasize a few things:

- http://www.ultracad.com/ has a few articles/tech notes on PCB 
layering, EMC et al. Well worth the read.

- You can easily do this design in a 2-layer, even if you need 20+ 
bits resolution. For comparison: more than a few semi-professional 
audio ADC designs get 20-22 bits out of a 2-layer design, usually 
limited by source/component noise and not interference/crosstalk.

- If you need really noise-free relays, consider using latching 
(electromechanical) relays. You only need to supply dirty digital 
current when switching; 'real' relays usually have much better 
coupling/distortion properties than semiconductor ones. Especially 
useful for settings that hardly ever change, like input attenuation 
or input selection

- It's not the switching frequency of digital signals that really 
matters, it's the edges (rise/fall times). Consider putting RC 
filters on digital lines, but mind (a) the max capacitive load of the 
output driver and (b) the max input current of the digital inputs on 
the net, combined with the difference between VOH/VOL of the drivers 
and VIH/VIL of the receivers. Reasonable safe rule of thumb: if your 
max cumulative Iin causes a voltage drop <= 0.1V over the R of your 
RC filter, you should be fine.

- Similarly, use the slowest logic family that works for your design. 
If a 74HC chip meets your timing requirements, don't use a 74LV chip.

- Use differential input signals. 'Nuff said.

- Use an antialiasing input filter; either simple passive RC/LC or an 
active opamp-based filter. Google for 'sallen key' for starters.

- Consider using a delta-sigma ADC, like the LTC2421 (single) / 
LTC2422 (dual). 20 bits resolution, built in notch filter settable 
for 50/60Hz (which will account for a large amount of your input 
noise).

- Keep related stuff close. Keep all digital lines short, and away 
from analog sections. If feasible, put your measurement circuit AT 
the signal source, especially with high-impedance sources. Either use 
a (differential) buffer amp, or even an ADC + ATtiny, and have a 
current loop to communicate with the digital system.

If you're seriously paranoid about digital signals, noise and plane 
placement, try to get your hands on "High-Speed Digital Design: a 
Handbook of Black Magic" by Howard Johnson 
(http://www.amazon.com/exec/obidos/ASIN/0133957241/qid=1047993447/sr=2-1/ref=sr_2_1/102-7913260-9216148). 
Title sums it all up, really ;-) I paid for my copy out of my own 
pocket and never regretted it. The author has quite a few interesting 
snippets at his web site (http://www.sigcon.com/publications.htm).

Do let us know how you get on (or not, if the regulars consider this 
way off-topic),

Regards,

JDB
[regular lurker, irregular poster]
--
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lart.tudelft.nl/