[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: General ground/power plane design questions

IMHO - worryiing about split ground planes for 12 bit low frequency
ADC's like this is overkill. A gorond plane will be plenty.
Goos artwork will achieve this in double sided - but you would
want to be making a lot of boards to justify the extra design time.

I'd guess most issues you have will come from:
1) noise on those current loop inputs (mains, hf, esd, mobile phones.. etc.
Do find space for the low passes people have mentioned.
I'd personally put clamp diodes to power rails in as well - perhaps
splitting the R part of the lpf in two and clamping there.
or supressors.
2) potential ringing on the SPI clock, if I understand your bussing correctly.
Series termination is usually a good choice - but does depend on topology.
(and tolerance on series terminators does not usually need 3 significant figures)

nothing else sounds challenging here.
john


Randall Nortman wrote:

Thank you to all who have responded! Your responses have been very
helpful indeed. I'm going to address a few questions/issues that came
up in many of the responses together here, and then reply separately
to a few particular issues.

First, several people asked about the ADC resolution. I'm using an
8-ch, 8-bit ADC built into the microcontroller (Atmel ATMega128) and
three peripheral 8-ch, 12-bit ADCs (Analog Devices AD7927). 12 bits
is probably overkill; 10 bits is enough even for those channels. (But
I didn't find any 10-bit ADCs that met my other requirements and were
any cheaper.)

All of the analog inputs come (over relatively long distances) from
4-20mA current loops. It seems to me that current loops should be
pretty noise-resistant, and voltage drops over the transmission lines
are irrelevant so long as the total load impedance remains within
spec. I have 120-ohm, 0.1% precision resistors on the board which
return these loops to ground, completing the loop and giving me a
0.48V-2.4V signal, referred to the analog ground on the board. These
feed into op-amp followers (LMC660s) to provide a high impedance to
the current loop and a low impedance to the ADCs. I have a precision
2.5V reference source for the ADCs, giving me 77% utilization of the
range of the ADCs (plus, I get a little resolution on under- and
over-range conditions, which is useful in my situation, because these
sensors will often swing somewhat outside of their range). To do
better, I'd need to use differential amps or differential ADCs to
subtract out the 0.48V baseline, which are relatively expensive and
would require more board space. (Differential inputs means fewer
channels per chip means more chips.)

Several people mentioned the problem with aliasing due to the ADC
sampling frequency. In my case, the sampling frequency will be
somewhat chaotic, which should reduce these effects. This is
because there's some multi-tasking happening on the CPU, and the ADC
sampling is just one task. Between each sample, it yields the CPU to
other tasks, and so lots of things (like communication on the
RS232/RS485 ports) can vary the exact sampling interval.

Still, I'm convinced that it would be worth trying to squeeze in some
one-pole RC low-pass filters. The problem is board space -- I'm
trying to put 24 analog inputs, 12 relays, two serial ports, and a CPU
on a 4"x5" board. The good news, I guess, is that SMT resistors and
capacitors are pretty small, so I can probably squeeze them in
somewhere. I'll probably have to move more components to the "back"
side of the board, though. (Which means no silkscreen to help place
those components, since I'm not paying for two-sided silkscreening.)

It seems to me that the best place for these filters is between the
op-amp followers and the ADC inputs. If I put them ahead of the
followers, then there's a lower impedance on the current loop, which
might influence the signal by providing a current path other than the
120-ohm resistors, right? (The LMC660 op-amps have very low input
bias current.) A capacitor won't sink a continuous current (beyond a
tiny leakage), but I'd be worried that it might create some sort of
resonance with the driver circuit on the other end of the loop.
Should I be worried about the same thing happening with the op-amps?


On the subject of splitting the power planes underneath the ADCs:

I double-checked the datasheet for the AD7927 -- there are several
AGND pins, one AVcc, and one VDrive (digital Vcc) pin -- no digital
ground pins. They advise against running digital traces under the die
and suggest separate analog and digital gound planes, connected at one
point as close to the chip as possible. Alas, I have 4 chips that
need both analog and digital, and I can't have the connection close to
all of them without causing other layout headaches. I guess, though,
that this means they only want the analog plane directly underneath
the die, not split analog/digital under different parts of the die.
(The microcontroller, which also has ADC channels, specifically
requests both planes under different parts of the chip, and supplies a
recommended layout.)


Thanks again for all your help! It's really wonderful for a lazy hack
like myself to be able to draw upon the expertise of so many competant
people. :)

Randall