Re: gEDA-user: Programming Altera FPGAs without Quartus

[Ales Hvezda <ahvezda@xxxxxxxx>]

Just jumping in here...

[snip]
>> I wasn't talking about the physical loading of the SOF into the chip, I
>> was talking about the *generation* of the SOF on the development host
>> from EDIF (Icarus Verilog output), i.e., the fitter, place and route,
>> and final SOF generator.
>>
>> MS

	Unfortunately, I doubt such a thing exists or will ever
exist from current FPGA devices.  Please see:

http://opencollector.org/news/Bitstream/

for a rather detailed answer (written/summarized by Graham Seaman).

-Ales