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Re: gEDA-user: VeriWell now on SourceForge



primorec wrote:


On 9/27/05, *Udi Finkelstein* <geda@xxxxxxxx <mailto:geda@xxxxxxxx>> wrote:


> simulator. So if you want to make a chip, you have to deliver a
Sorry, but you are out of date. Verilog XL is an interpretted simulator
that belongs in the Museum. Nobody is using it today.



hmm interesting observation... In the company I work (9000+ people), we can NOT
do our simulation without verilog-XL. It is very handy, convenient and nicely integrated into
our design flow, especially during mixed signal simulation ( Cadence Analog Artist ).


I have to talk to our CAD support group and check if we are really so much behind the curve ;)

Bit late, I know, but John Cooley has just published his DVCon05 report (http://www.deepchip.com/posts/dvcon05.html). He reckons that XL had 5% 'mindshare' in 2004, and 2% in 2005.


Evan