Re: gEDA-user: gPCB Polygon Best Practices

[Xtian Xultz <xultz@xxxxxxxxxxxx>]

Em Seg 30 Out 2006 15:33, Jeff VR escreveu:
> I spent the past few month becoming familiar with PCB and after
> finishing my schematic in gschem I'm ready to start the layout.
> Hooray!  I've got a fairly good handle on the basics but there are few
> areas that I need a little assistance/guidance.  The first is getting
> polygons and lines to play nicely together.  My plan is to try and get
> my design on a 2 layer board.  I've spent a lot of time arranging
> components to make routing as painless as possible.  If I can get away
> with 2 layers I want a GND plane on the bottom layer which will be
> split up by traces that just couldn't fit on the components side of
> the board.  So I did some practicing and drew a line for on the solder
> side of the board.  Afterwards I drew a large rectangle(polygon) on
> the solder side when I had GND_SLDR chosen .  I then figured out that
> <key>j enforced the clearances around the line and nicely removed the
> GND polygon from the trace.
>
> Problems/Questions:
> 1. Even after the polygon was cleared from the trace the rat's nest
> was claiming that the net associated with the trace on solder side was
> shorting with GND???  I remove the trace and the error goes away...if
> I leave the trace and remvoe the GND plane the error goes away.  How
> do I figure out what is wrong when visually the GND polygon is
> clearing the net?

I had a strange problem yesterday. I made two polygons that I wish to use to 
conduct large amount of current, and use thermals to connect them to the pins 
I wish. Everything was working just right, when PCB started to say a lot of 
shorts. I tryed everything, I deleted all the polygons, thermals, lines, 
started again, used lines instead of thermals, nothing. Then I closed PCB, 
opened again, andthe problem has gone, and I finished my board. The kind of 
bug really hard to track, because it didnt appeared again...

> 2. Should I draw the GND plane at the beginning or should it be the last
> step?

IMHO thats the last step. I must position the components thinking about the 
plane, draw the lines thinking on the plane, but only draw the plane when the 
stage is mounted. Draw the plane thinking about where the current will flow, 
how it will interfere on other lines, etc.

> 3. I have unplated holes on one of my symbols that is enforcing a
> clearance on the component side but not on the Solder side.  After I
> drew polygon associated with GND_SLDER I get warnings about a polygon
> to close to the holes.  Why is there not a clearance on the Solder
> side of the board enforced for nonplated holes?  How do I get this
> clearance around the holes to work?

Sometimes PCB gives a lot of warnings about polygons too close to pins, when I 
already made the pin connected to the polygon. 
The problem is that I never waste time looking exactly why PCB did so...

> 4. Layer assignments.  I understand that PCB goes up to 8 layers.  In
> the preferences there is  up to 8 groups and 8 different buttons two
> of which are unassigned by default.  If I changed my design to a 4
> layer design with the following configuration:
>
> Bottom (Layer 4): Signal and components
> Middle (Layer 3): GND
> Middle (Layer 2): VCC: 3.3, 5, and 12
> Top (Layer 1): Signal and components
>
> How would I configure the groups and Y axis buttons in PCB layer
> preferences to acheive the results above?  I saw in the info tab an
> example but I don't think it's exactly what I'm after.

By default, PCB creates 8 groups with one layer per group. If you want to make 
the board that way (you wrote above) just rename the layers you want to use 
with names you like, and go on. Of course, choose names like middle_vcc and 
middle_gnd or something like that.

> Any assitance is greatly appreciated.
>
> Thanks
> Jeff
>
>
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