Re: gEDA-user: QFP fan-out tips

[Randall Nortman <geda-lists@xxxxxxxxxxxxxxx>]

On Sat, Oct 06, 2007 at 07:21:22AM -0400, Bob Paddock wrote:
> 
> > I route power inwards under the chip, with vias to the power planes and
> > the decoupling cap on the other side.
> 
> Sometimes doing that adds enough inductance to cause problems,
> in high frequency boards.

What does "high frequency" mean?  I'm in the <50MHz range.  Do bigger
vias provide significantly less inductance than smaller ones?  I have
been trying to use big vias for my high-current connections, but maybe
that's just a waste of board space?

Speaking of vias -- Anybody have any experience putting them right
under an SMD pad?  I'm not thinking of doing that for the little 0.5mm
pitch pads (not enough room), but rather doing under 0603 or 0805
capacitor pads, to provide the connection to the plane layer.  That
would certainly save me some board space.  I also have a couple of
parts with exposed thermal pads, and the datasheets recommend vias
underneath the pad to conduct heat to the other layers.  But won't
this cause wicking of the solder to the underside of the board?  Is
there any way to get a little ring of soldermask around a via that's
in the middle of a pad?

DJ -- you mentioned using 0402 caps.  How tweezer-friendly are those?
I find I lose maybe 10% of 0603 parts as they fly out of the tweezers
and across the room.

Thanks to all for the good advice, as usual.

-- 
Randall


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user