gEDA-user: pcb, connecting to lonesome vias if Auto enforce DRC clearance is on

[Stefan Salewski <mail@xxxxxxxxxxxx>]

Next remark, sorry:

Currently I am connecting a RAM chip to an FPGA. Often I place vias
first, and then connect traces to these vias. If"Auto enforce DRC
clearance" is active, I can not connect traces to these "lonesome" vias,
so I have to deactivate "Auto enforce DRC clearance".

OK, routing around of "lonesome" vias, holding DRC clearance may be
useful, but connecting to then is in my opinion the more common case.
Can/should we modify pcb behaviour, i.e. connecting always to "lonesome"
vias (and to sub-traces which are still not connected to pads/vias) or
maybe connect only if crosshair/mouse is exactly over center of via or
only if SHIFT key is pressed?

Best wishes,

Stefan Salewski
 



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