Re: gEDA-user: pcb, connecting to lonesome vias if Auto enforce DRC clearance is on

[Ben Jackson <ben@xxxxxxx>]

On Wed, Oct 15, 2008 at 04:43:59PM +0200, Stefan Salewski wrote:
> 
> Currently I am connecting a RAM chip to an FPGA. Often I place vias
> first, and then connect traces to these vias. If"Auto enforce DRC
> clearance" is active, I can not connect traces to these "lonesome" vias,
> so I have to deactivate "Auto enforce DRC clearance".

Depending on which direction you are routing you can sometimes work around
this by mousing over where you want to go and hitting 'f' which will 'find'
that net which is then something you can bump into by auto-DRC rules.

As for temporarily defeating auto-drc to a via, I had considered it.  My
conclusion was that you could only allow direct (x,y exactly at the center
eg due to snapping) connection because otherwise you could "graze" the
lone via unintentionally.

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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