gEDA-user: About polygon clearances

[Eduardo Santana <electronics_questions@xxxxxxxx>]

Hello guys,

I'm new to the list, and also to the geda suite.

I've done a board using gscheme which I'll build at home after making the pcb with PCB. This is an image of it:

http://img508.imageshack.us/my.php?image=shot1he4.png

(please forget about some of the horrible routes and silk labels out of place, I've just finished routing the whole thing so it isn't finished yet)

I'd like to have on the gnd layer a rectangle covering the whole pcb which also respects routes, and which I'd be conecting to chasis ground (please correct me if I shouldn't be doing this, but I don't really like the idea of using all that copper as ground). I've noticed that for it to happen, the gnd layer needs to be on the same group that the component layer in this case.

However when I draw the rectangle, most of the ground layer doesn't appear, and I'd like somebody to tell me if this is a bug or not, and what could I do. Again, an image of the result:

http://img65.imageshack.us/my.php?image=shot2us9.png

If I try moving rectangle's vertices, it sometimes ends covering areas it should, it sometimes not. If I draw several rects on top of existing ones, the board will end up as it should (covering almost the whole board, except where distances are so small that clearance's policy properly apply), but then it becomes too slow, so I'm either doing something wrong, or god knows.

I've also tried several workarrounds/tests. For example if I clear one of the "offending routes" polygon-clear property, this is what happens:

http://img372.imageshack.us/my.php?image=shot3ss4.png

As you can see, things look a bit more as they should. Can someone tell me what's going on? I'm now using cvs version (checked out this morning with same results).

Many Thanks,

Eduardo.




      



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user