Re: gEDA-user: Eliminate separate Vcc planes?

[John Griessen <john@xxxxxxxxxxxxxx>]

Andy Fierman wrote:
> So your consultant thinks it's a bad idea to have a Vcc plane because
> it takes up space 
.
.
.

> Hopefully you can gently persuade your boss that this is not quite
> what the very expensive consultant meant to say.

So, are there no conditions where leaving out a VCC plane makes sense?
He might not have meant to compare to 3GHz motherboards.

If he meant to deal with RF transceivers as special case zones,
and the rest of the circuits operate below some clock speed like 600MHz,
I can imagine a stack up like:

for a four layer board...

signal  + VCC
=============
GND1
=============
signal2
=============
GND2
=============
signal3  + VCC2


or for a six layer board

signal1
=============
signal2
=============
GND1
=============
signal3
=============
GND2
=============
signal4
=============
signal5

for slower analog + VCC on 4,5
transmission lines on 3
switching + VCC2 on 1,2

Zones of power plane around mixed signal chips seem good sense -- they'd
act as pure capacitance and a place to hook bypass caps of various levels of
pure capacitance without hogging all the area.  And traces can be thick as you like --
1 cm wide...or so...

Now if we could just specify blind vias easily with pcb...

John



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