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Re: gEDA-user: Eliminate separate Vcc planes?
So your consultant thinks it's a bad idea to have a Vcc plane because
it takes up space that you could use for additional ground planes and
that you might need to run traces ...
... and then urges you to run power traces where?
In the - now empty - Vcc plane layer?
Or in the same layer as your already (according to your consultant)
full signal layers, leaving you a whole layer to put a shiny new
ground plane into?
Hmmm.
Suppose you have a 6 layer PCB with one continuous ground pane and one
continuous Vcc plane (dream on ...). It's not ideal but not everyone
wants to pay the extra for 8 layers.
layer 1 = signal (set up for 50R trace impedance w.r.t. ground plane)
:
small spacing
:
layer 2 = ground plane
:
small spacing
:
layer 3 = signal (set up for 50R trace impedance w.r.t. ground plane)
:
big spacing! (to minimise Xtalk between layers 3 to 4)
:
layer 4 = signal (set up for 50R trace impedance w.r.t. Vcc plane)
:
small spacing
:
layer 5 = power plane
:
small spacing (set up for 50R trace impedance w.r.t. Vcc plane)
:
layer 6 = signal
All the return currents for signals on layers 4 & 6 run over the power
plane until they get decoupled to layer 2 ground plane. Not ideal but
if the Vcc plane is properly decoupled to the ground plane with good
ceramic decouplers adjacent to all signal sources and destinations
(some of which may be dedicated and some shared Vcc decouplers anyway)
then that is OK.
(Note that with 6 layers you cannot gain much from the capacitance
between the ground and Vcc planes because you have two signal layers
sandwiched between them and so must keep those traces far enough apart
to keep the crosstalk between them negligible.)
And then you remove the plane from layer 5 ......
The return currents for layers 4 & 6 now run in layer 2 ground but the
trace impedances have skyrocketed because their image plane is now
many times further away.
Crosstalk between signals on layer 4 and on layer 6 is now huge
because it is proportional to 1/(1+(D/H)^2) where D is the spacing
between the adjacent traces on a layer and H is the height above the
image (ground) plane.
Crosstalk between signals on layer 6, 4 and 3 is now also huge because
they are no longer screened or effectively separated from each other.
Oh and you might be putting signals on layer 5 too?
The reduction of the total copper available to supply current to the
devices is slashed because it's only through individual traces.
Voltage drops increase due to the DC resistive losses. Dynamic voltage
drops increase due to the residual switching currents that the
discrete decoupling cannot remove being drawn through the increased
inductance and skin effect resistance of the supply traces rather than
a low inductance Vcc plane.
If you replace the Vcc plane with a ground plane then that would be
nearly ideal (assuming you properly via the two ground planes together
to keep the return path currents close to any signal vias that
transfer signals on traces referred to one ground plane to traces
referred to the other).
But if you could do that then wouldn't you have done it to start with?
As for the assumption that you put signal traces into a Vcc plane
layer. There are cases where you might have to but if you are so
worried about running out of routing space and can afford to replace
the power plane with a ground plane then you should not be putting
traces into that Vcc plane in the first place.
As you say, if your running stuff around in the GHz region then this
is just a nonsense. Even the very best ceramic caps still look
inductive much above 1GHz so they are still far from the ideal parts
you'd like to be able to sprinkle like fairy dust over all your noisy
parts and for you return paths.
As you mention; if you have a multi-rail system then you either have a
power plane layer that looks like the classic "Patchwork fields of
England" with lots of plane breaks (in which case you may have a
problem waiting to catch you out) or you already have a PCB with extra
layers in it to accommodate all these planes.
I can't see this advice catching on in many of those well known whizzy
processor motherboards.
Sorry if this seems like a bit of a rant or if you feel I have
offended your Grandmothers legendary egg sucking abilities but ...
Hopefully you can gently persuade your boss that this is not quite
what the very expensive consultant meant to say.
And I'll just go and calm down now.
Cheers,
Andy.
www.signality.co.uk
2009/10/19 Bob Paddock <graceindustries@xxxxxxxxx>:
> Boss just sent around something he got from a consultant on
> doing "proper" EMI design (which I've been doing for years already,
> I thought until consultant came up with this):
>
> "Eliminate separate Vcc planes.
> This ancient practice is long overdue for an overhaul. Years ago, the
> leaded capacitors were not able to provide a good enough short at VHF
> and above, so the reasoning was that the parallel plates of Vcc and
> ground made a good UHF capacitor. The problem with this is twofold:
> it takes away one or more ground planes, and more importantly doesn’t
> allow the designer to control where the noise current goes. Noise
> follows the path of least impedance, which may be anywhere on the PCB
> after you punch holes in the Vcc plane for vias and to route traces
> that have no other room to go. The best way to control noise is to
> use a separate trace for Vcc, and apply series and shunt elements to
> control the noise currents."
>
> There is no attribution as to were that advice comes from. The
> frequencies in question are 400 MHz to 3 GHz.
> To me running Vcc traces all over the board is the surest way to raise
> inductance etc., and seems wrong to me.
>
> Want to know what you thought of this consultants advice?
>
> Doesn't cover what happens in multi-rail systems either.
>
>
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