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Re: gEDA-user: Eliminate separate Vcc planes?



On Mon, Oct 19, 2009 at 03:18:25PM +0100, Andy Fierman wrote:
> So your consultant thinks it's a bad idea to have a Vcc plane because
> it takes up space that you could use for additional ground planes and
> that you might need to run traces ...
> 
> ... and then urges you to run power traces where?
> 
> In the - now empty - Vcc plane layer?
> 
> Or in the same layer as your already (according to your consultant)
> full signal layers, leaving you a whole layer to put a shiny new
> ground plane into?
> 
> 
> Hmmm.
> 
> Suppose you have a 6 layer PCB with one continuous ground pane and one
> continuous Vcc plane (dream on ...). It's not ideal but not everyone
> wants to pay the extra for 8 layers.
> 
> 
> layer 1 = signal (set up for 50R trace impedance w.r.t. ground plane)
>    :
> small spacing
>    :
> layer 2 = ground plane
>    :
> small spacing
>    :
> layer 3 = signal (set up for 50R trace impedance w.r.t. ground plane)
>    :
> big spacing! (to minimise Xtalk between layers 3 to 4)
>    :
> layer 4 = signal (set up for 50R trace impedance w.r.t. Vcc plane)
>    :
> small spacing
>    :
> layer 5 = power plane
>    :
> small spacing (set up for 50R trace impedance w.r.t. Vcc plane)
>    :
> layer 6 = signal

The problem is that you often have no choice with regard to layer
spacing. For 6 layers, low cost prototype quantity, my fab does
indeed have a large spacing in the middle, a small one between
layers 2 and 3 (and 4 and 5), and an intermediate one between the 
outer layer and the next one.

That's really messy for impedance control...

> All the return currents for signals on layers 4 & 6 run over the power
> plane until they get decoupled to layer 2 ground plane. Not ideal but
> if the Vcc plane is properly decoupled to the ground plane with good
> ceramic decouplers adjacent to all signal sources and destinations
> (some of which may be dedicated and some shared Vcc decouplers anyway)
> then that is OK.

Indeed.

	Gabriel


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