gEDA-user: iverilog FPGA examples

[Charles Lepple <clepple@ghz.cc>]

While poking around the verilog/examples directory, I noticed that initial 
values for registers don't seem to be handled anymore. To wit:

$ iverilog -txnf -ppart=XC4010XLPQ160 -pncf=clbff.ncf -oclbff.xnf clbff.v
clbff.v:61: warning: Process not synthesized.

I'm no XNF expert, but I checked the file, and didn't see anything that would 
imply that power-on values are being set for the registers.

I tried this with the head of the CVS code, and then backed off to the latest 
snapshot, and also tried v0_6_1. The only notable difference is that v0_6_1 
didn't emit a warning.

I don't have an immediate need for power-on register values, but the clbff.v 
file is somewhat misleading on this topic. 

Also, it doesn't appear that the FPGA target is generating NCF files. At 
least, I think I'm understanding this right: there used to be an "XNF" 
target, and now that it has been superceded by tgt-fpga/, the code in 
t-xnf.cc isn't being used.

Slightly off-topic: does anyone know offhand if fuse maps are freely available 
for Atmel's ATF750 PALs? (22V10 superset, 750 gates)

-- 
Charles Lepple <clepple@ghz.cc>
http://www.ghz.cc/charles/