gEDA-user: verilog question - modul parameter calculation

["hoyuka hoya" <hoyuka@xxxxx>]

Hello list members,

I'm new in verilog and I've started to learn it with iverilog (which is a
very excellent tool, I think).

So I'd like a modul with 3 parameters, but I'd love to calculate the 3rd
parameter from the first 2. Is it possible?

Here is a little code to demonstrate what I want:

// -----
module adder(a, b, res);

parameter aWidth=16;
parameter bWidth=16;
parameter resWidth=max(aWidth,bWidth)+1;

input [aWidth-1:0] a;
input [bWidth-1:0] b;
output [resWidth-1:0] res;
// -----

Se here I'd love to create an adder where the bit width of the operands
are parametrizable and I'd love to calculate the result's bit width
according to them. Is it possible? How?

Regards,
hoyuka
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