Re: gEDA-user: Ground flooding and DRC

[Ben Jackson <ben@xxxxxxx>]

On Sun, Sep 28, 2008 at 12:49:45PM +0200, David Kuehling wrote:
> 
> Unfortunately, flooding 0603 components results in a thin
> copper "hair" in between the pads, that is less than 6 mil and thus
> violates design rules.
> 
> http://mosquito.dyndns.tv/~spock/pcb-groundflood.png

Here is an etched PCB that illustrates what happens (ignore the soldermask,
that was my mistake):

	http://ad7gd.net/flex/custompcb-detail.jpg

(pic of the whole board is at http://ad7gd.net/flex/ )

Part of the problem is that our sub-1206 footprints could have a little
more clearance between them.  I just modified a 0603 so I could jump a
10/10 track on a homemade single-sided board.  You only need to go from
a 26mil gap between the pads to a 30mil gap.  I think that would be useful
for many reasons.

> The other problem is, that the DRC does _not_ detect the problem.

I don't think that's the right way to consider what happens when
clearances combine to make slivers in the copper.  What SHOULD happen
is that the polygon clearance code should eliminate those slivers and
then re-evaluate connectivity.  It's one thing to worry about a fab
complaining about the 6mil 'trace' (mine didn't) but it's another to
have the tool think that these slivers (which can get much thinner than
6mil!) constitute a connection that keeps an island of copper alive.

If you work on a board like the one I linked to above, you'll eventually
cut off islands of copper that are only connected by these slivers,
none of which can really be relied on to survive the etching process.
Even if the DRC flagged it, you'd have no way to fix it short of forcing
larger clearances to eliminate the stray copper.

I filed a bug on this about a year ago:

	[ 1751570 ] polygon plows should trim areas connected < min width

but I never came up with a way to fix it in PCB that wasn't going to
be verrry slow.

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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