Re: gEDA-user: Ground flooding and DRC

[David Kuehling <dvdkhlng@xxxxxx>]

>>>>> "Ben" == Ben Jackson <ben@xxxxxxx> writes:

> On Sun, Sep 28, 2008 at 12:49:45PM +0200, David Kuehling wrote:
>>  Unfortunately, flooding 0603 components results in a thin copper
>> "hair" in between the pads, that is less than 6 mil and thus violates
>> design rules.
>> 
>> http://mosquito.dyndns.tv/~spock/pcb-groundflood.png

> Here is an etched PCB that illustrates what happens (ignore the
> soldermask, that was my mistake):

> 	http://ad7gd.net/flex/custompcb-detail.jpg

Well, what causes the copper hairs to break?  Is it just over-etching,
or do fragments get loose and disappear (or move to parts of the board
where they aren't supposed to be)?

> (pic of the whole board is at http://ad7gd.net/flex/ )

> Part of the problem is that our sub-1206 footprints could have a
> little more clearance between them.  I just modified a 0603 so I could
> jump a 10/10 track on a homemade single-sided board.  You only need to
> go from a 26mil gap between the pads to a 30mil gap.  I think that
> would be useful for many reasons.

I had the same wish for running traces between pads.  With 6 mil traces
that actually works without modifying the footprints.  At least for
parts >= 0603.

> What SHOULD happen is that the polygon clearance code should eliminate
> those slivers and then re-evaluate connectivity.

Of course that would be much better.

> It's one thing to worry about a fab complaining about the 6mil 'trace'
> (mine didn't) but it's another to have the tool think that these
> slivers (which can get much thinner than 6mil!) constitute a
> connection that keeps an island of copper alive.

> If you work on a board like the one I linked to above, you'll
> eventually cut off islands of copper that are only connected by these
> slivers, none of which can really be relied on to survive the etching
> process.  Even if the DRC flagged it, you'd have no way to fix it
> short of forcing larger clearances to eliminate the stray copper.

I thought of using zero-width traces with non-zero clearance placed
below or around the footprint (somebody brought that up on this list,
some days ago).  But don't know yet what the DRC or gerber export is
going to think of zero-width traces.

> I filed a bug on this about a year ago:

> 	[ 1751570 ] polygon plows should trim areas connected < min
> width

> but I never came up with a way to fix it in PCB that wasn't going to
> be verrry slow.

Just thinking about it, would it be possible to erode a polygon?  ie
just thin it by 6 mil on all sides, by moving all sides 6 mil
perpendicular to the side's direction, then use the resulting eroded
polygon for connectivity analysis.  Well, getting the details right,
will be much more difficult than just that.

David
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