Re: gEDA-user: Driving the netlist from PCB (instead of gschem)

[DJ Delorie <dj@xxxxxxxxxxx>]

> Can't you verify the layout against the schematic netlist at any 
> time?

You can verify the pcb layout file against the schematics, yes.
Verifying the physical board against the schematics is much harder.
So, I've decided to always follow the "schematics first" ideal, for
both virtual and physical boards.

> By re-importing the netlist it would flag discrepancies between the
> current layout and the new netlist.  If they didn't agree I would
> find the problem and fix it.

PCB works the same way.

> If you don't want to we don't have to discuss this at all.  I think I 
> have been clear that there is an IPC proposed standard that is not 
> complete and has not been adopted by any vendors yet, even in its 
> initial stages.

I think it would be useful to look into that as an export format at
least, if/when people find they actually could benefit from it.  I
suspect we're too small a group to be "driving standards".

> Yes, that is my point exactly.  What IPC is doing can open the door 
> for a much greater degree of compatibility in EDA file formats and 
> program compatibility.  But this will happen only if the developers 
> want it to.   

Is there a publically (i.e. open) available copy of the proposed IPC
that we can look at?


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