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Re: gEDA-user: PCB format wishlist



On 09/06/2010 11:59 AM, Kovacs Levente wrote:
I'd add a capability of storing net information along with lines, polygons,
vias, and other copper objects. It would then make it unnecessary to have the
"new lines arcs clear polygons" stuff. A line in a polygon with the same
net wouldn't clear.

Levente
Hmm... this could be incorporated into
4) DRC re-use: refer to a 'base' DRC rule, rather than re-describing the DRC at every instance. DRC rules could be arbitrarily complex or simple, e.g. elements in DRC class '250V' must have a 0.050" clearance from class '5V', but can have 0.010" clearance within '250V', or something along the lines of the 'skinny, normal, fat, power' we have in place now.
A 'net' could be specified by a class/group of elements within which the DRC clearance would be 0 and probably the minimum intersection between two elements would be enforced as the minimum width for that group. If elements are tagged with a net ID, including polygons, then that would still take care of the 'new lines & arcs clear'.



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