Re: gEDA-user: Functional blocks and PCB format changes

[DJ Delorie <dj@xxxxxxxxxxx>]

> Will that mean every time something new is added to the core, each 
> set of import/export logic will break?  Or is that part of making 
> changes to the core, to update all affected functions?

Either the core's data structure will be flexible enough, or there
could be an intermediate layer that converts the core data into a
common format for the exporters.


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