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Re: Rep:Re: Rep:Re: [f-cpu] RC5, F-CPU and srotl

> The 12 cycle of the mul come from the bandwith (one result every 12
> cycle) of the unit. This unit aren't pipeline at all !
> Currently PIII have 1 cycle bandwith AND 1 clock latency (PIV have 2
> clock latency)

Ouch .. you say that P3 can do one mul per cycle ? It seems that
P4 makes multiplier two stage .. it lead me to conclusion that
Intel's NetBurst mean: pipeline everything to be able to raise
clock ..
It seems that current Pentiums are not so slow machines ..

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