Re: Rep:Re: Rep:Re: [f-cpu] RC5, F-CPU and srotl

[Yann Guidon <whygee@f-cpu.org>]

hi !

Nicolas Boulay wrote:
> I think you should sleep  ! ;p

to your big astonishment... i just woke up now :-)
I was being advandcing an article this morning and i couldn't
sleep before i solved a problem.

> The 12 cycle of the mul come from the bandwith (one result every 12
> cycle) of the unit. This unit aren't pipeline at all !
obviously.

> Currently PIII have 1 cycle bandwith AND 1 clock latency (PIV have 2
> clock latency)

how could they perform a 32-bit multiply in 1 cycle or two ???
Do they have such a large MUL unit ?

> nicO

then, Martin Devera wrote:
> > The 12 cycle of the mul come from the bandwith (one result every 12
> > cycle) of the unit. This unit aren't pipeline at all !
> >
> > Currently PIII have 1 cycle bandwith AND 1 clock latency (PIV have 2
> > clock latency)
> Ouch .. you say that P3 can do one mul per cycle ? It seems that
> P4 makes multiplier two stage .. it lead me to conclusion that
> Intel's NetBurst mean: pipeline everything to be able to raise
> clock ..
> It seems that current Pentiums are not so slow machines ..
> devik

Now that i read this, it strikes : nicO is not speaking about the multiply
but the add. it becomes obvious now !
Yes, P3 does a 32-bit add/sub in 1 cycle and P4 does it with 2 "minor" cycles
(in the "2x" clocked pipeline).
I don't have the new numbers for the multiplies, though.

Concerning their speed... don't you realize that the chips are getting
very expensive these days ? you usually pay for your performance, so
if your system is well balanced (enough memory bandwidth) it should be ok...


WHYGEE
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