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Re: [f-cpu] snapshot QDCPOC+YGASM



hi,

Juergen Goeritz wrote:
> On Thu, 2 Aug 2001, Michael Riepe wrote:
> > I have no problems with making the opcode either the LSByte or the MSByte
> > of the instruction, but we should stick with little-endian because
> > it's the default for the load and store instructions (without the `e'
> > flag set).  That is, if an instruction is stored at address (A), the
> > MSByte (which is probably the opcode) is stored at (A+3), and the
> > immediately following instruction starts at (A+4).
> 
> Hi,
> 
> may I rise another topic? What about providing a 'trace modul'
> in VHDL to split up the opcodes for debugging and tracing purposes?
i don't get this point. Can you explain more clearly ?

> In that case only the trace module and the instruction
> decoder must match. This is much easier to handle in automatic
> test suites. And I hope there is a test strategy to verify
> each modules interface to other parts. Can someone point me
> to this chapter in the documentation?

currently, in the VHDL sources, each execution unit is associated with
its own testbench. For the ROP2 unit, i have even written a little
interpreter that gets the test vectors from a text file so the testbench is
flexible. These individual testbenches are designed to verify the unit
against the expected behavious, during the unit's design.
However every units requires a specific strategy for testing.
ROP2 is simple but the multiplier for example is extremely complex.
On top of that, there is no precise strategy for chip validation
because it can depend too much on the implementation technology.
help is welcome :-)

> JG
WHYGEE
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