Re: [f-cpu] F-CPU vs ALPHA

[nicO <nicolas.boulay@ifrance.com>]

>FC0 issues in-order all the instructions that are considered as valid.
>if a trap occurs, it must NEVER enter the pipeline (because of the OOO
>completion, it would become a nightmare to rewind the pipeline !!!).

!!! "rewind the pipeline !" You just have to bypass the write back stage
!

>Currently, FC0 uses two addressing spaces : "private" space where the CPU
>is the only master (cache coherency is straight-forward) and "outside world"
>where all the accesses are in-order and uncacheable.

I don't think it will be very interresting (too slow). It will be much
interresting to manage this inside the VM unit by page (the page will
have the information of none caching, none registering,...). And then a
decoder will send the data thought memory port or fbus port.

>Use semaphores
>that are mapped in the SRs !

In all case, we need to write something in memory or to touch something
in the VM unit. So it's just pushing the problem away !


More generaly, i find the text very agressive against Alpha.(the 2 first
sentences of the text, for example). We should never forget that alpha
work since 10 years and fcpu is in it's very beginning. So this kink of
speech could make laught a futur investor in the fcpu, never forget
that.

nicO
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