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*To*: f-cpu@seul.org*Subject*: Re: [f-cpu] VHDL and delay estimation*From*: "gaetan@xeberon.net" <gaetan@xeberon.net>*Date*: Sat, 07 Feb 2004 03:27:04 +0100*Delivered-to*: archiver@seul.org*Delivered-to*: f-cpu-outgoing@seul.org*Delivered-to*: f-cpu@seul.org*Delivery-date*: Fri, 06 Feb 2004 21:25:25 -0500*In-reply-to*: <4024164F.8070603@stud.uni-hannover.de>*References*: <4023CB23.8070300@xeberon.net> <4024164F.8070603@stud.uni-hannover.de>*Reply-to*: f-cpu@seul.org*Sender*: owner-f-cpu@seul.org*User-agent*: Mozilla/5.0 (Windows; U; Windows NT 5.0; fr-FR; rv:1.6) Gecko/20040113

Michael Riepe a écrit :

if (EffSub = '1') then My := not My; grs := not grs; end if;I would count it as d=2, t=2 from any of the three signals.

ok that much!!

and for: if (ReprB (REPRES_NORMALISED) = '1') then Mb(M_SIZE) := '1'; else Mb(M_SIZE) := '0'; end if; ?Rewritten: Mb(M_SIZE) := ReprB (REPRES_NORMALISED); No additional delay from ReprB (REPRES_NORMALISED).

ok

in fast, s will be the sticky bit, ie the or on every droped bit by the shifter (used latter by the rounding step). But i have a stage between... so will the reduce_or function on a max 24bit vector (or 53) fit in one stage? I think so but i'm not sure...next one:

how much this function cost

procedure fpu_rshift(F : in std_ulogic_vector; N: in std_ulogic_vector;

G : in std_ulogic_vector;

Y : out std_ulogic_vector; B : out std_ulogic_vector;

s : out std_ulogic

) is

constant LF : natural := F'length;

constant LN : natural := N'length;

constant LY : natural := Y'length;

constant LB : natural := B'length;

constant LG : natural := G'length;

constant L : natural := LG+LF+LB;

variable gg : std_ulogic_vector(LG-1 downto 0) := G;

variable ff : std_ulogic_vector(LF-1 downto 0) := F;

variable yy : std_ulogic_vector(L-1 downto 0);

variable ss : std_ulogic;

constant default_bit : std_ulogic := '0';

begin

yy(L-1 downto LB) := gg(LG-1 downto 0) & ff(LF-1 downto 0);

yy(LB-1 downto 0) := (others => default_bit);

ss := '0';

for i in 0 to LN-1 loop

if (N(i) = '1') then

-- reduce_or need a vector with size 4.n

if i=0 then

ss := ss or yy(0);

elsif i=1 then

ss := ss or yy(0) or yy(1);

else

ss := ss or reduce_or(yy(2**i-1 downto 0));

end if;

yy(L-2**i-1 downto 0) := yy(L-1 downto 2**i);

yy(L-1 downto L-2**i) := (others => default_bit);

end if;

end loop;

Y := yy(LF+LB-1 downto LB);

B := yy(LB-1 downto 0);

end procedure

Too much. Shifting itself takes d=LN/t=LN (wire delay not counted) but the successive calculation of `ss' is too heavy. Its delay becomes higher with every step of i, for a total of approximately d=16/t=16 when LN=6.

The shifter is really long... I don't see any way to improve it (for the version without the ss calculation).it's the right shifter (N is at max 6 bit sized)

it also the same thing as

if (N(0) = '1') then

yy(L-1) := G;

yy(L-2 downto 0) := F(L-1 downto 1);

else

yy := F;

end if;

[...]

if (N(5) = '1') then

yy(L-1 downto L-31-1) := (others => G);

yy(L-32-1 downto 0) := yy(L-1 downto 32);

end if;

The true question is: after these 3 steps (MSB, not and shift) do i have enought place to put a n-bit half adder (1xor deep)...????

I don't think so. Actually, if you calculate `ss' like this, it won't fit even without the half adder. But I don't know what's around the circuit. Maybe there is room somewhere else.

Again, thanks for your help, F-team!

Michael. ************************************************************* To unsubscribe, send an e-mail to majordomo@seul.org with unsubscribe f-cpu in the body. http://f-cpu.seul.org/

-- ~~ Gaetan ~~ http://www.xeberon.net ************************************************************* To unsubscribe, send an e-mail to majordomo@seul.org with unsubscribe f-cpu in the body. http://f-cpu.seul.org/

**Follow-Ups**:**Re: [f-cpu] VHDL and delay estimation***From:*Michael Riepe <michael+fcpu@stud.uni-hannover.de>

**References**:**[f-cpu] VHDL and delay estimation***From:*"gaetan@xeberon.net" <gaetan@xeberon.net>

**Re: [f-cpu] VHDL and delay estimation***From:*Michael Riepe <michael+fcpu@stud.uni-hannover.de>

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