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Re: [f-cpu] VHDL and delay estimation

Hi #3,

gaetan@xeberon.net wrote:
in fast, s will be the sticky bit, ie the or on every droped bit by the shifter (used latter by the rounding step). But i have a stage between... so will the reduce_or function on a max 24bit vector (or 53) fit in one stage? I think so but i'm not sure...
It should. The reduce_or function has a "logarithmic" delay of d=log(N)/log(x) if gates with x inputs are used (N = number of input bits).


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