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[f-cpu] Re: generic adder

i forward this message to the mailing list it may interest some people ...

Michael Riepe a écrit :

Bonjour Gaetan!
Hallo Michael!

I would like to know if there is a easy way to get A+B and A+B+2 results instead of A+B and A+B+1 with your generic adder and the csv and cla funcitons. I need it for rounding to infinity mode in my floating point adder.

The generic adder can not calculate A+B+2 directly.
ok dream ends here... :)

I have in one stage 4x16 bit adders and in the next one carry look ahead logic you told me.
I have some literatures saying a row of half adder should be included before the adder (and i don't really understand how it will work since it only half adders..), but in this case the half adders + 4x16 bit generic adders will not fit in one stage...

That's a problem, right. Concerning your first question (how it works): Consider two additional vectors, AA and BB, which are the same width as A and B. Now let

I blocked a long time 'cause i didn't shifted the carry vector and of course it didn't worked......

AA := A xor B;
BB := lshift(A and B, 1);

AA + BB will be the same as A + B (modulo 2**N). Due to the left shift, BB(0) is zero. By setting it to 1, you can increment the result by 1 before the operands enter the adder, and once again by using the `incremented' output of the adder. But beware, this is slow, since BB(0) has to pass the whole adder.
in fact there is a trick: BB(0) is set to 0 and we extract the LSB of AA (to a L=a0 xor b0 bit) and set this LSB to '1'. Now, considering the value of L we got:
if L=0, we have A+B+1 and A+B+2 from the output of your adder. A+B can be obtained from A+B+1 setting the LSB (which will be '1') to '0'.
and if L=0, the adder gives A+B and A+B+1. Since the LSB of A+B+1 will be '0', setting it to '1' will produce A+B+2.

That's why i wanted to know if there is a way to get both A+B and A+B+2 results playing with PP and GG vectors...

I currently see no way to do that. On the other hand, I do not understand why you need to increment the result by 2. In any case, the truncated result and the rounded result will differ by 1 (at the least significant digit). They have to, if you want to be IEEE compliant.
In fact, in effective addition, rounding to + infinity mode and positive number (or rounding to -infinity mode and negative number), overflow from the compound adder, and (LSB+g+r+s)='1', we need to select A+B+2 ("round up at position [L-1]"). and if we only change the Carry bit (not overflow), we just have round up at position L (so we take the A+B+1 result)...
LSB is the LSB of the A+B result, g,r are the guard bit (the 2 last bits dropped by the right shifter), and s is the sticky bit ('or' on every other dropped bits)...

Thanks you very much Micheal ;-)



~~ Gaetan ~~

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