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Re: [f-cpu] Re: generic adder


Michael Riepe a écrit :


Hi #4,

gaetan@xeberon.net wrote:
[...]
In fact, in effective addition, rounding to + infinity mode and positive number (or rounding to -infinity mode and negative number), overflow from the compound adder, and (LSB+g+r+s)='1', we need to select A+B+2 ("round up at position [L-1]"). and if we only change the Carry bit (not overflow), we just have round up at position L (so we take the A+B+1 result)...

Wait a minute... you want to handle adding, carry-out and rounding at the same time? Like this:

My := Ma + Mb;
Mz := Ma + Mb + 1; -- incremented adder output
not really:
Mx and Mz are output of adder, but they are (Ma+Mb and Ma+Mb+1) or (Ma+Mb+1 and Ma+Mb+2) result

    if (carry_out = '1') then
        round_up := My(LSB) or g or r or s;
        if (round_up = '1') then
            My := Mz + 1; -- double increment
it's not an increment it's only a bit replacement '1' -> '0' or '0' -> '1' following L

        end if;
        My := rshift(My, 1, '1');
        Ey := Ey + 1;
    else
        round_up := g or r or s;
        if (round_up = '1') then
            My := Mz;
        end if;
    end if;

Right? I'm afraid you'll have to increment Mz one more time in that case.
It's almost that. but no additionnal incrementation is requiered since we know the LSB
In fact, everything is explained in the document:
http://citeseer.nj.nec.com/bruguera98rounding.html
pdf : http://citeseer.nj.nec.com/rd/20864957%2C397604%2C1%2C0.25%2CDownload/http://citeseer.nj.nec.com/cache/papers/cs/19153/http:zSzzSzwww.ac.usc.eszSzfileszSzarticuloszSz2000zSzgac2000-i04.pdf/bruguera98rounding.pdf


In fact the code currently looks like:

-- right shifting
if (FT = t_single) then
fpu_rshift(Mb(M_SIZE downto 0), DE(4 downto 0), "0",
My(M_SIZE downto 0), grs(2 downto 1), grs(0));
else
fpu_rshift(Mb(M_SIZE downto 0), DE(5 downto 0), "0",
My(M_SIZE downto 0), grs(2 downto 1), grs(0));
end if;

Mx(M_SIZE downto 0) := Ma(M_SIZE downto 0);

-- bit inverter;
if (EffSub = '1') then
My := not My;
grs := not grs;
end if;

-- n bit half adder
fpu_half_adder(Mx(M_SIZE downto 0), My(M_SIZE downto 0), Mcc(M_SIZE downto 0), Mss(M_SIZE downto 0));
-- save LSB
ll := Mss(0);
-- replace LSB by '1'
Mss(0) := '1'; --S(0) should always be '1'
-- save carry out
cc := Mcc(M_SIZE);
Mcc(M_SIZE downto 1) := lshift(Mcc(M_SIZE downto 1),1); -- lshit carry vector by 1
Mcc(0) := '0';

-- next is the compound adder
=> outputs Man and Manp1
There is a huge controle bit calculation to select if i need S, Sp1 or Sp2 result (following rounding mode, sign,...)
S = Ma + Mb
Sp1 = Ma + Mb + 1
Sp2 = Ma + Mb + 2
The only thing to be done is correct the LSB of Man or Manp1 (following state of the control bits) and we get
the correct output (S, Sp1 or Sp2)...

Check the pdf it is better explained. This is what i'm trying to implement into my fadder (with models from other documents).


Michael.

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--

~~ Gaetan ~~
http://www.xeberon.net


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