Delay (was:Re: [f-cpu] SIMD and exception)

[Nicolas Boulay <nico@seul.org>]

Le Lundi 9 Février 2004 21:36, Michael Riepe a écrit :
<...>
> which takes 3 inverters and an and-or-invert (AOI) gate, resulting in
> d=2/t=2. But on the other hand, you wrote "xor", so the synthesizer may
> create just that.
>
> I suggest you use work.misc.xor3 (available for both std_ulogic and
> std_ulogic_vector) if you need a 3-input XOR. It's easier to adapt a
> single function to the target than to scan the whole F-CPU for stray
> 3-input XORs.
>
> On the other hand, if you *know* that one of the inputs arrives late,
> you can as well use
>
> 	Y := (A xor B) xor C;	-- when C arrives late
>

It's much better to write "A xor B xor C". Synthetiseur are really good to 
balance tree of signal's, if you write something else you over constraint it.

If you use and/or/not gate, it will hardly find the away to use the xor gate 
if available. But from the "xor" statement it will find the better way to 
produice a xor without a xor cells.

We should code at the highest level as possible, most of the time, the 
synthetiseurs will more clever than us. And it will adapt the better code for 
the technology available which is impossible to do by hand.

nicO
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