Re: Tr:Rep:Re: [f-cpu] "Tree"

[Kim Enkovaara <embo@mpoli.fi>]

> crapy C-style VHDL : to much heavy ! SystemC 2.0 is
> quite nice and intriduice concept as channel,
> interface, port and events. This stuff are really
> usefull for specification for Hardware as for
> software. You could create your simulator then refine
> it until to understand what is better to put in
> hardware or software (for example : how much
> automative must be the SRB).

I think biggest problem with SystemC style approach is that it is quite
different compared to the real design process of many products. It's quite
academic thinking that the product is first defined with some system
language and only after that the implementation starts. 

For example if the product has an ASIC the ASIC design starts quite much
before other designers even know about the product. ASIC design usually
takes that 1.5-2 years. USW/higher level SW guys are still in their old
projects during the start of ASIC phase. And ASIC is the critical path
usually in products. If you design the system at system SW level before
ASIC project it usually means substantial amount of system level code.
Even if that code is directly usable in the end product the TTM is longer.
ASIC project can be started later because the system description takes so
long time. On the other hand if the ASIC is specified in done
with traditional means and system SW design for example starts at the same
time, time is saved.

I think the real question is can the time used in system interface
optimization saved in later stages of design. Usually competent designers
can do quite good HW/SW interface (fortunately this list has HW guys :)).
Can you really save the time needed to fix some HW quirks in SW by using
much more time to design the interface.

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