Re: [f-cpu] "Tree"

[Kim Enkovaara <embo@mpoli.fi>]

> for programing this stuff. Nobody has a good RTL language
> developed. I don't want to have * / in a RTL language if
> I can't specify addc and overflow and carry out from addition
> if I want it. I once had a old yellow book on RTL languages

Why do you normally need to specify how the arithmetic is performed. Isn't
it enough to tell the synthesizer what are the timing constraints and
synthesizer selects from its arithmetic toolbox "optimal" solution that
meets the timing. Currently some hints (pragmas etc. in the code) might be
needed to instruct the synthesizers if they get confused. And I think
synthesizers are in their infancy still at higher level optimization. 

I think same applies to state machines. I consider state machines done
even with RTL level. And if the SM is done in RTL I think the
synthesizer should select the coding of the state vectors etc. Usually it
has better knowledge about the constraits of the architecture and what
creates fastest solution. Optimal solution I think is higher level SM
description where you only draw states and tell state transition rules
etc. The problem is how to rely that high level description directly to
synthesis level. Usually that high level SM is converted to RTL code,
after that the synthesizer reads the RTL code and sees that it is a SM, 
and optimizes it at high level again.

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