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Re: [f-cpu] Coding for Synthesis
Hi,
Michael Riepe wrote:
>On Wed, Jul 10, 2002 at 06:35:12PM +0200, Just an Illusion wrote:
>[...]
>
>>if rising_edge... is well but the syntax
>>
>>if (clock_signal'event and clock_signal='1') then ...
>>
>>is better (see synopsys recommendation coding style)
>>
>
>Since Synopsys understands either version, and the *correct*
>incantation reads
>
> if clock_signal'event
> and clock_signal = '1'
> and clock_signal'last_value = '0' then ...
>
That is not a supported declaration format for clock edge specification,
for information you can see the IEEE 1076-93 (Vhdl LRM) and the IEEE
P1076.6-2001 (Vhdl RTL LRM, the IEEE-1076.6 give same things on the
subject).
>
>I prefer the shorter form.
>
>>and for falling_edge
>>
>>if (clock_signal'event and clock_signal='0') then ...
>>
>
>We do not use falling edge clocks, negative logic and the like.
>
>[...]
>
>>> BTW: It is considered good style to write one process per
>>> pipeline stage (unless the pipeline is `forked'), and put the
>>> `if rising_edge(clock_signal)' clause at the very end of the
>>> process, as shown.
>>>
>>BTW (2) : It is considered good style to write one process to drive only
>>one signal.
>>
Sorry I have forget to add "in case of edge-sensitive sequential logic"
>
>And replicate everything that's common? No, thank you.
>
The code replication can be fastidious but that can help the synthesizer
to give a better netlist.
>
>
>*Who* recommends this, BTW?
>
By example : Synopsis, Symplicity, Examplar...
This is not a mandatory condition but it can help synthesis :-)
@+
Just an Illusion
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