Re: [f-cpu] Conditionnal Load and Store

[Yann Guidon <whygee@f-cpu.org>]

hi,

Christophe Avoinne wrote:
> ----- Original Message -----
> From: "Michael Riepe" <michael@stud.uni-hannover.de>
> To: <f-cpu@seul.org>
> Sent: Monday, July 29, 2002 12:30 AM
> Subject: Re: [f-cpu] Conditionnal Load and Store
> 
> > `jump' has a free bit, and we can free one in `move' if we make sign
> > extension a separate operation.

if it is possible to use the proposed 4-bit version of the condition field,
i'll integrate it.

> > Another option is to make `move' a full-word operation (that is, no
> > size bits at all, like jump) and reconsider `widen' for sign and zero
> > extension. That way, we can use 6 bits for the condition code.
i don't remember what the options for MOVE are.

however i have separated MOVE from CMOVE because CMOVE
requires an additional condition field. Although these fields
are cleared in a normal MOVE, the separate opcode might be critical
for later architectures.

> If we consider that registers are always 64-bit wide (or 256-bit wide),
> 'move' does not need to have size-bits. I always thought that size-bits
> usually apply for load and store operations not for registers by themselves.
> Sign or zero extension should be done with 'widen', since its name is not
> misnamed :).

maybe the size bit can have special uses in move.
but the context is not fresh in my head.

WHYGEE
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