Le 2015-03-30 10:28, Nicolas Boulay a ÃcritÂ:
Beside that, there is
always a missing mode or feature, so cpu must then be used. I think
that a kind of specialised (one cycle) instructions are prefered, even
with it's own "power domain".
"one cycle" is not really possible with modern ultra-pipelined CPU.
"one instruction" can be done if it is sufficiently generic (let's
keep it RISC) and small. For other purposes, the choice of interface
depends indeed on the size of the dataset. In your example of AES,
it fits well into fixed blocks of 256 bits and it can be a pretty
intensively used feature so it makes sense for Intel to add it,
as well as other features like CRC32 and RNG.
For more complex operations, there is the big old hairy complex problem
of interruptions, errors and restart. AES, CRC and RNG don't throw
Other "complex accelerators" might encounter problems,
for example TCP/IP.
Writing this reminds me that I had examined such a system, indeed !
Short version : a handled game console fits most of the criteria I listed above
Â- small, so relatively inexpensive,
Â- graphics require tons of computations, we can hack accelerators too,
Â- low-power, real-time, embedded design
Â- has a "kernel" side and runs third-party "applications" (games)
I don't say we should start a gaming company. I mean :
this is the kind of realistic target system that could
both prove the points we make with F-CPU (freedom etc.)
AND test our designs against.