Re: [f-cpu] Bit Shuffler (Take 2)

[Michael Riepe <michael@stud.uni-hannover.de>]

On Fri, Sep 28, 2001 at 12:46:03PM +0300, Kim Enkovaara wrote:
[...]
> I hate to dissapoint you, but this new version is slower. It got 56MHz in
> the synthesis run for the same chip. I'll try to run the whole Xilinx flow
> to the different versions at some point. But the synthesis results usually
> correlate quite well to the actual results. Especially if some
> floorplanning is done.

Hmm...  maybe I should try something different.  Can you please synthesize
the attached file?  It's a self-contained 64-bit 'rotate right' entity
with explicit and/or gates which may become the new Shuffle64 core --
if it's fast enough.

I'm afraid we're hitting the `6 gates' rule with the bit shuffling
unit, no matter how we implement it.  Maybe we should add a second
stage to the `bitwise' pipeline (shift/rot/bitrev operations).

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
-- rotate64.vhdl -- 64-Bit Rotate Right
-- Copyright (C) 2001 Michael Riepe <michael@stud.uni-hannover.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

-- $Id$

library IEEE;
use IEEE.std_logic_1164.all;

entity Rotate64 is
	port (
		A : in std_ulogic_vector(63 downto 0);
		B : in std_ulogic_vector(5 downto 0);
	--
		Y : out std_ulogic_vector(63 downto 0)
	);
end Rotate64;

architecture Behave_1 of Rotate64 is
	function decode_3_8 (A : in std_ulogic_vector(2 downto 0))
						 return std_ulogic_vector is
		variable yy : std_ulogic_vector(7 downto 0);
	begin
		yy := (
			7 =>     A(2) and     A(1) and     A(0),
			6 =>     A(2) and     A(1) and not A(0),
			5 =>     A(2) and not A(1) and     A(0),
			4 =>     A(2) and not A(1) and not A(0),
			3 => not A(2) and     A(1) and     A(0),
			2 => not A(2) and     A(1) and not A(0),
			1 => not A(2) and not A(1) and     A(0),
			0 => not A(2) and not A(1) and not A(0),
			others => 'X'
		);
		return yy;
	end decode_3_8;

	function rotr64 (A : in std_ulogic_vector(63 downto 0);
					 B : in std_ulogic_vector(5 downto 0))
					 return std_ulogic_vector is
		variable sel1 : std_ulogic_vector(7 downto 0);
		variable sel8 : std_ulogic_vector(7 downto 0);
		variable yy : std_ulogic_vector(63 downto 0);
		variable t : std_ulogic;
		variable k : natural;
	begin
		sel1 := decode_3_8(B(2 downto 0));
		sel8 := decode_3_8(B(5 downto 3));
		for i in yy'range loop
			t := '0';
			for j in A'range loop
				k := (64 - i + j) rem 64;
				t := t or (A(j) and sel1(k rem 8) and sel8(k / 8));
			end loop;
			yy(i) := t;
		end loop;
		return yy;
	end rotr64;
begin
	Y <= rotr64(A, B);
end Behave_1;

-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please