Re: gEDA-user: Lines which are not clears poligon

[Tamas Szabo <sza2king@xxxxxxxxxxx>]

DJ Delorie wrote:
>> The latter one have a strange behavior. The most problematic that some 
>> of the lines not clears the rectangle used for filling the unused area 
>> by copper. Unfortunately DRC does not show any error or warning although 
>> there a many short circuit due to the rectangle.
> 
> Looks like a bug to me.  Ben?  Can you look at this one?

2c2
< # date:    Mon Apr 28 22:23:41 2008
---
 > # date:    Mon Apr 28 21:57:39 2008
2609c2609,2610
< 	Line[385000 232500 377500 232500 1000 2000 "clearline"]
---
 > 	Line[385000 232500 380000 232500 1000 2000 "clearline"]
 > 	Line[380000 232500 377500 232500 1000 2000 "clearline"]
2616c2617,2618
< 	Line[370000 225000 377500 232500 1000 2000 "clearline"]
---
 > 	Line[370000 225000 375000 230000 1000 2000 "clearline"]
 > 	Line[375000 230000 377500 232500 1000 2000 "clearline"]

Huh. Finally it solved (but it still can be a bug). In the wrong file 
there is two additional lines. If I remove them everything goes right. 
These additional lines are exactly on the top of other lines.

How did I found it? Cut all lines to buffer, remove copper field, 
created a new copper area and paste the buffer. Than it was correct.

> 
>> Additionally the copper (size: 0.1mm, 0.1mm, w-0.1mm, h-0.1mm) surrounds 
>> the mounting hole in case of the control.pcb, but not for the io.pcb.
> 
> Use the thermal tool to change that.
> 
>> Furthermore am I right that ClrFlag(selection, join) should switch on 
>> clearance for all selected lines? But it seems it is not working for me. 
> 
> It should.
> 
> 
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> 



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