Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

[Andy Peters <devel@xxxxxxxxx>]

On Mar 8, 2007, at 2:47 PM, Christoph Lechner wrote:

> Andy Peters schrieb:
> > It might be easier to work backwards, from the schematic, and have  
> > it back-annotate into the .ucf (user constraint file), which is  
> > the file used by the Xilinx tools for pinouts (and timing specs,  
> > etc etc).
> It's true that ripping off everything exept the pairing
> 	Pin Names <-> Pin Numbers
> from the gschem symbol is a snap compared to building/
> updating a symbol from the Fitter report. But how would
> you make sure that the user of gschem doesn't put an input
> pin at an reserved location, i.e. a JTAG or PWR pin.

I guess we're talking about creating symbols that are CPLD-design  
specific, so that pin names will change with the design.  This is as  
opposed to creating generic symbols, as noted in my other e-mail in  
this thread.  Generic symbols have the vendor-assigned pin name which  
includes information about pin type, such as differential pairs,  
global/regional clocks, config pins, etc.

To answer the question. One of two ways:

a) Have Yet Another Attribute attached to the symbol pins that would  
throw up an error if a user attempted to attach a "regular" signal  
wire to one of the reserved pins.

b) Assume that the gschem user is not an idiot, and is actually  
looking at the vendor-provided pinout tables while deciding which  
pins to assign.  I just got through doing this last week for a 100- 
pin VQFP Xilinx FPGA.  This might be the simplest approach.  I had  
the schematic and layout windows up and a printout of the pinout  
diagram, and assigned pins based on how it routed while also noting  
the pin type.

Of course, what would be cool is if after this all completed, it  
would back-annotate to the .ucf.  A guy can dream ...

> The timing issues following from forcing the Xilinx tool
> to use a user-defined pin-out are non-trivial IMHO, at
> least for CPLDs. So I guess it would be better regarding
> timing issues to run Xilinx ISE (or another vendor's tool)
> first and then go to gschem and create/update the symbol.

For older architectures, it was definitely a requirement that you let  
the tools assign the pins.  But in my recent designs, using  
CoolRunner CPLDs and Spartan IIE and 3E and Acex FPGAs, I assign pins  
as needed by the layout, and I've never had problems meeting timing,  
nor have I had fitting issues.

The XC3000 and 95xx parts are dead!

> The (at the moment) missing link between logic design
> tools and gschem is a big show-stopper for the gEDA
> suite, I guess.

Commercial tools charge big bucks for this missing link, and it's  
still not ideal.

-a



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user