Re: gEDA-user: Design Flow Roadmap starting point

[DJ Delorie <dj@xxxxxxxxxxx>]

> From PCB, I would like to seperate the hierarchy from the rest of
> the refdes. I would like to be able to layout a hierarchical
> section. I would like to be able to save that section as a seperate
> collection. I would like to be able to paste a copy of that section
> into a larger pcb layout and only have to change the top of
> hierarchy string to correctly interact with the netlist.

PCB doesn't care what the refdes is, a heirarchical one is just as
valid as a common one.  I have a RenumberBlock() action that's
designed to make it easier to have repetetive blocks on a board, but I
think you want something more automatic, like the way element data is
grouped as an element.  For example, have a block on the board that is
a modular entity.  Normally, you can't do anything but move it around
as a whole.  A special action "opens" this block (and hides everything
else) so you can edit it.  When you're done, it's closed again - and
any copies of the block are automatically updated in place.

The usual buffer to/from file mechanism should be sufficient
(gui-wise) for saving blocks as files.

Have you tried using Xfig's group/ungroup/editgroup mechanism?

> I would like to be able in the netlist to tell pcb which slots are
> swapable, which i/o pins are swapable and which pin pairs can
> function as differential pairs (these last two have to be able to be
> limited to specific banks) such that pcb could correctly change the
> net list itself. Then I would like PCB to be able to tell me what
> pins and in what order the pins were swapped so that this could be
> imported back into the original design.

This is the usual back-annotation request, for starters.  If we can
propogate the slotting information to pcb, perhaps we can figure out a
GUI to swap them.

> While I am at it. PCB should be able to do hidden vias, buried vias
> and micro vias...

If we can get the "layer types" project done (this is listed as the
non-copper layers project in SoC), we'll be able to have a concept of
a "layer stack" (unless we just assume the physical stack matches the
GUI layer layout).

The next project after that is what I call a "multi-pin", which is a
standard pin, but with a much more intense copper description, one for
each layer, with drill depth parameters et al.  That would include
blind and buried vias.  Microvias is just a drill size after that,
unless you need them called out in a different .cnc file.

> Did I mention the ability to cut out areas of
> layers such that I can resese components into lower layers?

Assuming you know a fab that can mill layers before assembling
them... is that what you're talking about?  That would mean having
elements and pads on layers other than the outer two, yes?


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