Re: gEDA-user: Icarus Verilog with Xilinx simprims...

["CSB" <csb_cbw@xxxxxxxxxxx>]

> If you're doing an asynchronous design, then you're on your own!   
> Current CPLD and FPGA methodologies don't lend themselves well to  
> async design.

> Certainly the fitted design will have glitches, as delays through  
> various paths will be different.  The point of synchronous design is  
> that you can ignore those glitches; all you care about is if the  
> inputs to all of your registers are settled by the setup time before  
> the clock edge.  And for each clock, that is what the static timing  
> analyzer tells you -- the length of all paths through all registers.   
> As long as the prop delay from register A through logic to the D  
> input of register B is less than the clock period, you win.  The  
> timing analyzer accounts for register clock-to-out delay and register  
> input setup and hold.

> If your design is purely combinatorial, then of course you will have  
> glitches, and remember that a post-fit timing simulation will show  
> you these glitches for the particular routing the tools just used,  
> which may change for each place-and-route run as you tweak the  
> design. 

Hmm. My design is a bit wacky... it's mostly clock-based, but also has
a combinatorial part. I'll test what I have with a real CPLD, see if
it'll
work (or not). Good thing they're erasable, I feel it's not the last
time I'm going to re-write it !


> http://iverilog.wikia.com/wiki/Graffiti#SDF_support
Quite interesting, thank you for the link.


Thanks to all for the information,
Christian
-- 
  CSB
  csb_cbw@xxxxxxxxxxx

-- 
http://www.fastmail.fm - A fast, anti-spam email service.



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user