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Re: gEDA-user: Icarus Verilog with Xilinx simprims...



CSB wrote:

If your design is purely combinatorial, then of course you will have glitches, and remember that a post-fit timing simulation will show you these glitches for the particular routing the tools just used, which may change for each place-and-route run as you tweak the design.

Hmm. My design is a bit wacky... it's mostly clock-based, but also has a combinatorial part. I'll test what I have with a real CPLD, see if it'll work (or not). Good thing they're erasable, I feel it's not the last time I'm going to re-write it !

When they said warnings and "your on your own" that means when you make something "just barely function" and have no safety margin logically coming form the spec sheet of the parts you used, you do not know when it will or won't work, at which temperature, or on which individual part from the factory.

John G


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