[f-cpu] little update before i get asleep

[Yann Guidon <whygee@f-cpu.org>]

hi,

i have revised some details in the drawing.
i have taken account of the RegSet write latency
and i have moved the FF before the Wbar Write MUX.

HOWEVER i have encountered a "big" problem.
when moving the "issue" part to overlap the Xbar,
i have forgotten a little scheduling detail :
When stalled (for register availability reasons)
the instruction MUST be held at decode stage,
not Xbar. This is because the Current_Instruction (buffer)
is held identical, so the register set
read address doesn't change, and we don't have
to care about the order in which the data get ready.

If we stall at Xbar read, it gets hairy...

ok, let's shut this computer down and sleep(night).

WHYGEE
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