Re: [f-cpu] Register Bank - reset, partial write

[nicO <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hi, and thanks to Stéphane for the hints,
> 
> Michael Riepe wrote:
> >
> > On Thu, Aug 02, 2001 at 10:09:11PM +0200, turlututu@bechamail.com wrote:
> > [...]
> > >       Some vendors (ST micro, IBM, Atmel, ...) seem to dislike
> > > asynchronous resets in designs. They strongly prefer synchronous
> > > resets. Resets are managed in a unique module but we have to modify
> > > sequential processes; the original code is :
> > [...]
> >
> > >       Note that the use of a constant for the reset value is the best way
> > > because you don\'t always know if the reset is active high or low before the
> > > choice of a vendor.
> > >       Do not forget that a majority of vendors do not support tri-states
> > > ( \'Z\' ) in the core of a design, so we have to replace them with muxes.
> >
> > This is only a case study, not the real code.
> >
> > On the other hand, coding hints are welcome.  Thank you :)
> 
> it seems that we have found another code reviewer, cool ! :-P
> 
> > >       Could somebody tell me why there are
> > > \"Write_0, Write_1, Write_Enable_0, Write_Enable_1\"
> > > signals in the sensitivity list ?
> >
> > Because some tools complain if they're not present.  I don't know why;
> > as far as I understood, only Clk is needed in a sequential circuit with
> > no asynchronous controls (which you just confirmed, somehow).
> 
> while we're at it, can you try to see what is necessary to have
> "partial register write" ?
> The current FC0 study requires the ability to write specifically
> to the following : bits 0-7, 8-15, 16-31, 32-47, 48-63 (5 subfields).
> the interface to the register set specifies 2x register
> address (6 bits each) and 5 bits for each address, counting as
> "write enable" for the subfields...
> 
> Concerning the register set reset, it can probably be performed
> with some "tricks" : "hard" reset is probably not necessary.
> i think that a "smart" use of the scheduler can trigger a burst
> of register writes after a reset. what do you think ? :-)

I think that reset on the register bank isn't necessary (flipflop with
rest are much bigger and if we use SRAM cell there is no reset at all).
Otherwise partial write could (8 bit none SIMD write) be usefull for
power comsumption consideration (8 cells with clk instead of 64, it
could save a lot of power...)

nicO

> 
> >  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
> WHYGEE
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