Re: [f-cpu] Register Bank

[Yann Guidon <whygee@f-cpu.org>]

hi again (again) ((again))....

Michael Riepe wrote:
> On Fri, Aug 03, 2001 at 03:55:18AM +0200, Yann Guidon wrote:
> [...]
> > while we're at it, can you try to see what is necessary to have
> > "partial register write" ?
> More control lines ;-P
i guess so :-)

> > The current FC0 study requires the ability to write specifically
> > to the following : bits 0-7, 8-15, 16-31, 32-47, 48-63 (5 subfields).
> Why 32-47 and 48-63?  IMHO the slices must look this way:
> 
>         A:  7 downto  0         enable: '1'
>         B: 15 downto  8         enable: U(0) or SIMD
>         C: 31 downto 16         enable: U(1) or SIMD
>         D: 63 downto 32         enable: U(2) or SIMD
> 
> In 8-bit mode, only A is written; A+B in 16-bit mode, A+B+C in 32-bit
> mode, and A...D in 64-bit mode.  Note that this corresponds directly
> to the encoding of the chunk size control lines in the EU interfaces
> (the U08, U16 and U32 lines, or the U vector in later versions).  I
> knew that encoding was a pretty good choice :)

you forget a little detail... it's called "loadcons" and it loads
16-bit chunks in each fourth of a register.
hehe, i've thought about this details for a long time ;-)

> > the interface to the register set specifies 2x register
> > address (6 bits each) and 5 bits for each address, counting as
> > "write enable" for the subfields...
> I'd rather stick to the decoded enable lines for now (let's assume that
> there are three 6-to-64 decoders in the IF/ID, one for each possible
> register operand -- that's probably cheaper than 5 decoders inside the
> register bank).  In any case, we need an additional `U' vector for
> each write port (3 lines per port).  The read ports can work at full
> width all the time, can't they?

ooops, i was not thinking about the read ports.
Of course, the 3 read ports work at full width all the time.
There are these 3x 6-to-64 decoders for reading at decode stage.

The write ports can benefit from the short pipelining : the 6-to-64 decoding
can be performed during the Xbar Write cycle :-) That's where we can probably
include the 5 write enable lines in each write port.


> > Concerning the register set reset, it can probably be performed
> > with some "tricks" : "hard" reset is probably not necessary.
> > i think that a "smart" use of the scheduler can trigger a burst
> > of register writes after a reset. what do you think ? :-)
> Didn't we want to include a POST (Power-On Self Test) anyway?
yup.

> Since that will have to test the registers (i.e. write into them and read back the
> values), it can also initialize them.  I removed the Rst line now ;)
yo !

> Please have a look at the attachment.
i am a bit surprised by the technique you use.
could it be simpler without the use of functions ?

i also question about the use of 6-to-64 decoders : some
register banks are designed with the "usual" array but some
are also designed with multiplexors.

> CU
with great pleasure :-)
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/