Re: [f-cpu] Scheduler

[Yann Guidon <whygee@f-cpu.org>]

hello,

nicO wrote:
> A much more explicit scheme, i hope ;p

it's a bit better... but the picure is even larger
and i can't display it completely. i don't understand
all the signal meanings and types either, and some
parts are detached from the rest, i don't see what their
use and place is...

Is it possible to meet and discuss about it ?

> nicO
> 
> nicO a écrit :
> >
> > I send you a scheme of a bypass net.
> >
> > The "Active" signal is the number of the active unit. On the same
> > pipeline stage, there is only one active unit. For each active stage, i
> > compare the address of the 2 write registers to the 2 registers in use
> > by the instructions of the stage. I only drawn the system for one
> > register (not the 3 read register) and only for one pipeline stage.
> >
> > I try to make a more clear one.
> >
> > nicO
> >
> >   ------------------------------------------------------------------------
> >  [Image]
> 
WHYGEE
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