Re: [f-cpu] Scheduler

[nicO <nicolas.boulay@ifrance.com>]

A much more explicit scheme, i hope ;p

nicO

nicO a écrit :
> 
> I send you a scheme of a bypass net.
> 
> The "Active" signal is the number of the active unit. On the same
> pipeline stage, there is only one active unit. For each active stage, i
> compare the address of the 2 write registers to the 2 registers in use
> by the instructions of the stage. I only drawn the system for one
> register (not the 3 read register) and only for one pipeline stage.
> 
> I try to make a more clear one.
> 
> nicO
> 
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